Load–store architecture - Wikipedia

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In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).^1: 9–12 

Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.^1: 9–12 

For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.^1: 9–12 

The earliest example of a load–store architecture was the CDC 6600.^1: 54–56  Almost all vector processors (including many GPUs ²) use the load–store approach.³

See also

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• Load–store unit
• Register–memory architecture

References

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Footnotes

1. ^ Jump up to: ^{a b c d} Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design. Jones & Bartlett Learning. ISBN 0867202041. ↩ ↩² ↩³ ↩⁴

2. ^ “AMD GCN reference” (PDF). ↩

3. ^ Harvey G. Cragon (1996). Memory systems and pipelined processors. Jones & Bartlett Learning. pp. 512– 513. ISBN 0867204745. ↩